Historically, lithographic scaling has generally been achieved by means of increasing the numerical aperture available for optical exposure equipment, and by means of using shorter exposure wavelengths. At present, the industry has reached a condition in which it is no longer possible to economically increase numerical aperture or reduce the exposure wavelength. As a result, many alternative methods of scaling integrated circuit lithography are being investigated. One method involves the use of multiple exposures to form a single lithographic mask pattern on the wafer. The pitch of the pattern is split by interstitially placing a line from a second mask in between two lines formed by a first mask. The effective pitch of the resulting combined pattern can be twice as dense as that of a single pattern. This density enhancement can provide a path for continued device scaling. However, in order to gain this density, it is necessary to aggressively trim the linewidth printed at each layer. If a conventional over-exposure of a positive resist film is used to trim the line, the process window becomes very small. We have developed an alternative method of trimming the linewidth such that the process window can be maintained without degradation during the trim. We have demonstrated the incorporation of our trim process into a pitch-split double-patterning scheme for the patterning of semiconductor circuits.
Chang et al., United States Patent Application Number 20060257749 A1 describe some of the problems associated with chemical trim processes such as submerging a patterned photoresist layer and the entire wafer substrate in a basic or neutral chemical solution which results in removal of a portion of the photoresist layer and causes a reduction in the “critical dimension.” The exact reduction of the “critical dimension,” however, is difficult to control which often results in over-trimming or removal of the photoresist layer. Moreover, after treatment with the chemical solution, the properties of the sidewalls of the photoresist change, which affect the etch resistance of the photoresist. Examination of the sidewalls by SEM after the etch will detect any significant damage, but the SEM process itself can also affect the etch resistance of the sidewalls.
Chang et al. also describe some difficulties using a plasma trim process in which a photoresist layer on semiconductor wafer is exposed to plasma etching to by means of ion bombardment to trim the layer in order to reduce the “critical dimension.” Plasma trim processes usually result in undesirable line-end trimming that prevents maintaining a predetermined line length. Relatively long plasma trim processes also reduce the yield of useful photoresists, changes the properties of the exposed photoresist, and also results in having to redeposit photoresist material in adversely affected areas.